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fn6560 rev.7.00 page 1 of 20 sep 26, 2015 fn6560 rev.7.00 sep 26, 2015 isl28133 single micropower, chopper stabilized, rrio operational amplifi er datasheet the isl28133 is a single micropower, chopper stabilized operational amplifier that is optimized for single supply operation from 1.8v to 5.5v. its low supply current of 18a and wide input range enable make it an excellent general purpose op amp for a range of applications. the isl28133 is ideal for handheld devices that op erate off 2 aa or single li-ion batteries. the isl28133 is available in the 5 ld sot-23, the 5 ld sc70, and the 6 ld 1.6mmx1.6mm tdfn packages. all devices operate over the extended temperature range of -40c to +125c. related literature ? an1480 ?ISL28133ISENSEV1Z evaluation board user?s guide? ? an1499 ?isl28133eval1z high-gain evaluation board user?s guide? features ? low input offset voltage . . . . . . . . . . . . . . . . . . . . . . 8v, max. ? low offset tc . . . . . . . . . . . . . . . . . . . . . . . . 0.075v/c, max ? input bias current. . . . . . . . . . . . . . . . . . . . . . . . . . 300pa, max. ? quiescent current . . . . . . . . . . . . . . . . . . . . . . . . . . .18a, typ. ? wide supply range . . . . . . . . . . . . . . . . . . . . . . . . . 1.8v to 5.5v ? low noise (0.01hz to 10hz). . . . . . . . . . . . . . . . . . 1.1v p-p , typ. ? rail-to-rail inputs and output ? operating temperature range. . . . . . . . . . . .-40c to +125c applications ? bidirectional current sense ? temperature measurement ? medical equipment ? electronic weigh scales figure 1. typical application circuit figure 2. vos vs temperature bidirectional current sense amplifier i-sense+ 0.1 4.99k 4.99k 499k 499k 3 4 5 2 1 isl28133 + - v+ v- gnd v sense out v ref v s 1.8v to +5.5v i-sense- -6 -4 -2 0 2 4 6 8 10 -40-200 20406080100120 temperature (c) v os (v) median min max n = 67
isl28133 fn6560 rev.7.00 page 2 of 20 sep 26, 2015 block diagram in- v+ in+ v- + - + - clock gen + drivers main amplifier v out 5khz crossover filter part number (note 1) part marking package (rohs compliant) pkg. dwg. # isl28133fhz-t7 (note 2) bcfa (note 5) 5 ld sot-23 p5.064a isl28133fhz-t7a (note 2) bcfa (note 5) 5 ld sot-23 p5.064a isl28133fez-t7 (note 2) bha (note 5) 5 ld sc70 p5.049 isl28133fruz-t7 (note 3) (no longer available, recommended replacement: isl28133fhz-t7 ) t8 6 ld tdfn l6.1.6x1.6 ISL28133ISENSEV1Z evaluation board isl28133eval1z evaluation board isl28133csensev1z evaluation board notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ specia l pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). in tersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requir ements of ipc/jedec j std-020. 3. these intersil pb-free plastic packaged products employ specia l pb-free material sets; molding compounds/die attach materials and nipdau plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-f ree soldering operations. intersil pb-free pr oducts are msl classified at pb-free peak reflow temperatures that meet or ex ceed the pb-free requirements of ipc/jedec j std-020. 4. for moisture sensitivity level (msl), please see the device information page for the isl28133 . for more information on msl please see techbrief tb363 . 5. the part marking is located on the bottom of the part.
isl28133 fn6560 rev.7.00 page 3 of 20 sep 26, 2015 pin configurations isl28133 (5 ld sot-23) top view isl28133 (5 ld sc-70) top view isl28133 (6 ld tdfn) top view out v- in+ v+ in- 1 2 3 5 4 +- in+ v- in- v+ out 1 2 3 5 4 + - 1 2 3 6 4 5 out v- in - v+ nc in + + - n o l o n g e r a v a i l a b l e o r s u p p o r t e d pin descriptions isl28133 (5 ld sot23) isl28133 (5 ld sc-70) isl28133 (6 ld tdfn) pin name function equivalent circuit 3 1 4 in+ non-inverting input circuit 1 2 2 2 v- negative supply 4 3 3 in- inverting input (see circuit 1) 141outoutput circuit 2 5 5 6 v+ positive supply 5 nc not connected ? this pin is not electrically connected internally. in- v+ in+ v- + - + - clock gen + drivers v+ v- out
isl28133 fn6560 rev.7.00 page 4 of 20 sep 26, 2015 absolute maximum rating s thermal information max supply voltage v+ to v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5v max voltage vin to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 6.5v max input differential voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5v max input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma max voltage vout to gnd (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5v esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3000v machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200v charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500v thermal resistance (typical) ? ja (c/w) ? jc (c/w) 5 ld sot-23 (note 6, 7) . . . . . . . . . . . . . . . . 225 110 5 ld sc-70 (note 6) . . . . . . . . . . . . . . . . . . . 206 n/a 6 ld tdfn (note 6). . . . . . . . . . . . . . . . . . . 240 n/a maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 6. ? ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 7. for ? jc , the ?case temp? location is taken at the package top center. electrical specifications v + = 5v, v - = 0v, vcm = 2.5v, t a = +25c, r l = open, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +125c . parameter description conditions min (note 8) typ max (note 8) unit dc specifications v os input offset voltage -8 2 8 v -15.5 15.5 v tcv os input offset voltage temperature coefficient 0.02 0.075 v/c i os input offset current -60 pa i b input bias current -300 30 300 pa -600 600 pa common mode input voltage range v+ = 5.0v, v- = gnd -0.1 5.1 v cmrr common mode rejection ratio vcm = -0.1v to 5.0v 118 125 db 115 db psrr power supply rejection ratio vs = 2v to 5.5v 110 138 db 110 db v oh output voltage swing, high r l = 10k ? 4.965 4.981 v v ol output voltage swing, low r l = 10k ? 18 35 mv a ol open loop gain r l = 1m ? 174 db v + supply voltage (note 9) 1.8 5.5 v i s supply current r l = open 18 25 a 35 a i sc+ output source short circuit current r l = short to ground or v+ 13 17 26 ma i sc- output sink short circuit current -26 -19 -13 ma ac specifications gbwp gain bandwidth product f = 50khz a v = 100, r f = 100k ??? r g =1k ??? r l = 10k ?? to v cm 400 khz
isl28133 fn6560 rev.7.00 page 5 of 20 sep 26, 2015 e n v p-p peak-to-peak input noise voltage f = 0.01hz to 10hz 1.1 v p-p e n input noise voltage density f = 1khz 65 nv/ ? (hz) i n input noise current density f = 1khz 72 fa/ ? (hz) f = 10hz 79 fa/ ? (hz) c in differential input capacitance f = 1mhz 1.6 pf common mode input capacitance 1.12 pf transient response sr positive slew rate v out = 1v to 4v, r l = 10k ? 0.2 v/s negative slew rate 0.1 v/s t r , t f , small signal rise time, t r 10% to 90% a v = +1, v out = 0.1v p-p ? r f =0 ??? r l = 10k ??? c l =1.2pf 1.1 s fall time, t f 10% to 90% 1.1 s t r , t f large signal rise time, t r 10% to 90% a v = +1, v out = 2v p-p ? r f =0 ??? r l = 10k ??? c l =1.2pf 8s fall time, t f 10% to 90% 10 s t s settling time to 0.1%, 2v p-p step a v = +1, r f = 0 ??? r l =10k ??? c l = 1.2pf 35 s notes: 8. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. 9. parts are 100% tested with a minimum operat ing voltage of 1.8v to a vos limit of 15v. electrical specifications v + = 5v, v - = 0v, vcm = 2.5v, t a = +25c, r l = open, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +125c . (continued) parameter description conditions min (note 8) typ max (note 8) unit typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open. figure 3. average input offset voltage vs supply voltage figure 4. v os vs temperature, v s = 1.0v, v in =0v, r l =inf 0.5 1.0 1.5 2.0 2.5 3.0 3.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 supply voltage (v) average vos (v) +25c n = 67 -40c 125c -12 -10 -8 -6 -4 -2 0 2 4 6 8 -40 -20 20 40 60 80 100 120 temperature (c) v os (v) 100 80 0 min max n = 67 median
isl28133 fn6560 rev.7.00 page 6 of 20 sep 26, 2015 figure 5. v os vs temperature, v s = 2.5v, v in =0v, r l = inf figure 6. i b + vs supply voltage vs temperature figure 7. i b - vs supply voltage vs temperature figure 8. ios vs supply voltage vs temperature figure 9. average supply current vs supply voltage figure 10. min/max supply current vs temperature, v s = 0.8v, v in = 0v, r l = inf typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open. (continued) -6 -4 -2 0 2 4 6 8 10 -40 -20 0 20 40 60 80 100 120 temperature (c) v os (v) median min max n = 67 -50 0 50 100 150 200 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 supply voltage (v) ibias in+(pa) +125c n = 12 +25c +75c +100c -40c -50 0 50 100 150 200 250 1.52.02.53.03.54.04.55.05.5 supply voltage (v) ibias in- (pa) n = 12 +100c +125c +75c +25c -40c -80 -70 -60 -50 -40 -30 -20 -10 0 10 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 supply voltage (v) average ios (pa) +125c n = 67 +25c -40c 16 17 18 19 20 21 22 23 24 25 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 supply voltage (v) average supply current (a) +25c n = 67 -40c +125c 14 16 18 20 22 24 26 28 -40 -20 0 20 40 60 80 100 120 temperature (c) supply current (a) median min max n = 67
isl28133 fn6560 rev.7.00 page 7 of 20 sep 26, 2015 figure 11. min/max supply current vs temperature, v s = 2.5v, v in = 0v, r l = inf figure 12. input noise voltage 0.01hz to 10hz figure 13. input noise volt age density vs frequency figure 14. input noise curr ent density vs frequency figure 15. frequency response vs open loop gain, r l = 10k figure 16. frequency response vs open loop gain, r l = 10m typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open. (continued) 14 16 18 20 22 24 26 28 30 -40 -20 0 20 40 60 80 100 120 temperature (c) supply current (a) median min max n = 67 time (s) input noise voltage (nv) -600 -400 -200 0 200 400 600 800 0 102030405060708090100 v+ = 5v r l = 100k rg = 10, rf = 100k av = 10,000 c l = 3.7pf frequency (hz) 10 100 1000 input noise voltage (nv/?hz) 0.001 0.01 0.1 1 10 100 1k 10k 100k v+ = 5v av = 1 frequency (hz) 0.01 0.1 1.0 0.001 0.01 0.1 1 10 100 1k 10k 100k input noise current (pa/?hz) v+ = 5v av = 1 -100 -50 0 50 100 150 200 1 100 10k 100k 1m 10m open loop gain (db)/phase () frequency (hz) rl = 10k simulation cl = 100pf gain phase 1k 10 100m 10m 1m 0.1m -100 -50 0 50 100 150 200 open loop gain (db)/phase () frequency (hz) r l = 10m simulation c l = 100pf gain phase 1 100 10k 100k 1m 10m 1k 10 100m 10m 1m 0.1m
isl28133 fn6560 rev.7.00 page 8 of 20 sep 26, 2015 figure 17. gain vs frequency vs r l, v s = 1.6v figure 18. gain vs frequency vs r l, v s = 5v figure 19. gain vs frequency vs feedback resistor values r f /r g figure 20. gain vs frequency vs v out, r l = open figure 21. frequency response vs closed loop ga in figure 22. gain vs frequency vs supply voltage typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open. (continued) -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 frequency (hz) normalized gain (db) 10k 100k 1m 10m 1k 100 v+ = 1.6v av = +1 v out = 10mv p-p c l = 3.7pf r l = 1k r l = 10k r l = 49.9k r l = 100k r l = open -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 frequency (hz) normalized gain (db) 10k 100k 1m 10m 1k 100 v+ = 5v av = +1 v out = 10mv p-p c l = 3.7pf r l = 100k r l = 1k r l = 10k r l = open r l = 49.9k 0 1 2 3 4 5 6 7 8 9 10 100 1k 10k 100k 1m frequency (hz) normalized gain (db) v+ = 5v r l = 100k av = +2 v out = 10mv p-p c l = 3.7pf r f = r g = 100k r f = r g = 10k r f = r g = 1k -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 10k 100k 1m 10m frequency (hz) normalized gain (db) v+ = 5v r l = open av = +1 c l = 3.7pf 1k 100 v out = 10mv v out = 100mv v out = 1v v out = 250mv v out = 500mv -10 0 10 20 30 40 50 60 70 10 100 1k 10k 100k 1m 10m frequency (hz) gain (db) av = 1 av = 10 av = 100 av = 1000 v+ = 5v v out = 10mv p-p c l = 3.7pf r l = 100k r g = 10k, r f = 100k r g = 100, r f = 100k r g = 1k, r f = 100k rg = open, r f = 0 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 frequency (hz) normalized gain (db) 10k 100k 1m 10m 1k 100 r l = 100k av = +1 v out = 10mv p-p c l = 3.7pf v+ = 1.6v v+ = 3.0v v+ = 5.5v v+ = 1.2v
isl28133 fn6560 rev.7.00 page 9 of 20 sep 26, 2015 figure 23. gain vs frequency vs c l figure 24. cmrr vs frequency, v s = 5v figure 25. psrr vs frequency, v s = 5v figure 26. cmrr vs frequency, v s = 1.6v figure 27. psrr vs frequency, v s = 1.6v figure 28. cmrr vs temperature, vcm = -2.5v to +2.5v, v+ = 2.5v typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open. (continued) frequency (hz) normalized gain (db) -10 -8 -6 -4 -2 0 2 4 6 8 10k 100k 1m 10m 1k 100 v+ = 5v r l = 100k av = +1 v out = 10mv p-p c l = 824pf c l = 224pf c l = 474pf c l = 51pf c l = 3.7pf c l = 104pf cmrr (db) 100 1k 10k 100k 1m 10m frequency (hz) 10 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 v+ = 5v r l = 100k av = +1 vcm = 1v p-p c l = 16.3pf psrr (db) 100 1k 10k 100k 1m 10m frequency (hz) 10 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 psrr- psrr+ v+ = 5v r l = 100k av = +1 v cm = 1v p-p c l = 16.3pf cmrr (db) 100 1k 10k 100k 1m 10m frequency (hz) 10 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 v+ =1.6v r l = 100k av = +1 v cm = 1v p-p c l = 16.3pf psrr (db) 100 1k 10k 100k 1m 10m frequency (hz) 10 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 psrr- psrr+ v+ = 1.6v r l = 100k av = +1 v cm = 1v p-p c l = 16.3pf 80 100 120 140 160 180 200 -40-200 20406080100120 temperature (c) cmrr (db) median min max n = 67
isl28133 fn6560 rev.7.00 page 10 of 20 sep 26, 2015 n figure 29. psrr vs temperature, v+ = 2v to 5.5v figure 30. large signal step response (4v) figure 31. large signal step response (1v) figure 32. small signal step response (100mv) figure 33. v out high vs temperature, r l = 10k, v s +-2.5v figure 34. v out low vs temperature, r l = 10k, v s +-2.5v typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open. (continued) 75 85 95 105 115 125 135 145 155 -40 -20 0 20 40 60 80 100 120 temperature (c) psrr (db) median min max n = 67 time (s) large signal (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 50 100 150 200 250 300 350 400 v + = 5v r l = 100k a v = 1 c l = 3.7pf v out = 4v p-p time (s) large signal (v) 0 0.2 0.4 0.6 0.8 1.0 1.2 0 102030405060708090100 v + = 5v r l = 100k a v = 1 c l = 3.7pf v out = 1v p-p time (s) small signal (v) 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0 5 10 15 20 25 30 35 40 v+ = 5v r l = 100k av = 1 c l = 3.7pf v out = 100mv p-p 4.972 4.974 4.976 4.978 4.980 4.982 4.984 4.986 -40 -20 0 20 40 60 80 100 120 temperature (c) v out (v) median min max n = 67 0.016 0.017 0.018 0.019 0.020 0.021 0.022 0.023 0.024 -40 -20 0 20 40 60 80 100 120 temperature (c) v out (v) median min max n = 67
isl28133 fn6560 rev.7.00 page 11 of 20 sep 26, 2015 applications information functional description the isl28133 uses a proprietary chopper-stabilized architecture shown in the ?block diagra m? on page 2. the isl28133 combines a 400khz main amplifier with a very high open loop gain (174db) chopper stabilized amplifier to achieve very low offset voltage and drift (2v, 0.02v/c typical) while consuming only 18a of su pply current per channel. this multi-path amplifier architec ture contains a time continuous main amplifier whose input dc offset is corrected by a parallel-connected, high gain chopper stabilized dc correction amplifier operating at 100khz. from dc to ~5khz, both amplifiers are active with dc of fset correction and most of the low frequency gain is provided by the chopper amplifier. a 5khz crossover filter cuts off the low frequency amplifier path leaving the main amplifier active out to the 400khz gain-bandwidth product of the device. the key benefits of this architecture for precision applications are very high open loop gain, very low dc offset, and low 1/f noise. the noise is virtually flat across the frequency range from a few mhz out to 100khz, except for the narrow noise peak at the amplifier crossover frequency (5khz). rail-to-rail input and output (rrio) the rrio cmos amplifier uses parallel input pmos and nmos that enable the inputs to swing 100mv beyond either supply rail. the inverting and non-inverting inputs do not have back-to-back input clamp diodes and are capable of maintaining high input impedance at high differential input voltages. this is effective in eliminating output distortion caused by high slew-rate input signals. the output stage uses common source connected pmos and nmos devices to achieve rail-to-rail output drive capability with 17ma current limit and the capability to swing to within 20mv of either rail while driving a 10k ? load. in+ and in- protection all input terminals have internal esd protection diodes to both positive and negative supply rail s, limiting the input voltage to within one diode beyond the suppl y rails. for applications where either input is expected to exceed the rails by 0.5v, an external series resistor must be used to ensure the input currents never exceed 20ma (see figure 35). layout guidelines for high impedance inputs to achieve the maximum performance of the high input impedance and low offset voltage of the isl28133 amplifiers, care should be taken in the circuit board layout. the pc board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resi stance on the board. high gain, precision dc-coupled amplifier the circuit in figure 36 implements a single-stage, 10kv/v dc-coupled amplifier with an input dc sensitivity of under 100nv that is only possible using a low vos amplifier with high open loop gain. this circuit is practical down to 1.8v due to it's rail-to-rail input and output capa bility. standard high gain dc amplifiers operating from low vo ltage supplies are not practical at these high gains using typical low offset precision op amps because the input offset voltage and temperature coefficient consume most of the available output voltage swing. for example, a typical precision amplif ier in a gain of 10kv/v with a 100v v os and a temperature coefficient of 0.5v/c would produce a dc error at the output of >1v with an additional 5mvc of temperature dependent error. at 3v, this dc error consumes > 30% of the total supply voltage, making it impractical to measure sub-microvolt low frequency signals. the 8v max v os and 0.075v/ c of the isl28133 produces a temperature stable maximum dc output error of only 80mv with a maximum temperature drift of 0.75mv/ c. the additional benefit of a very low 1/f noise corner frequency and some feedback filtering enables dc voltages and voltage fluctuations well below 100nv to be easily detected with a simple single stage amplifier. figure 35. input current limiting - + r in r l v in v out figure 36. high gain, precision dc-coupled amplifier - + 100 r l v in v out 1m 1m 100 -2.5v +2.5v a cl = 10kv/v c f 0.018f
isl28133 fn6560 rev.7.00 page 12 of 20 sep 26, 2015 long term v os drift figure 37 shows a plot of daily v os drift measurements of 30 individual isl28133 amplifiers over a continuous 572 day period at +25c. the 30 units were connected in a gain of 10k, mounted on a single pc board and kept at room temp. the 30 amplifier outputs were measured daily by a dvm and scanner under computer control. the daily v os measurements were subtracted from the initial v os value to calculate the v os shift. the test board was powered from a ups to maintain uninterrupted power to the test units. three instances of lost measurement data ranging from 2 days to 2 weeks due to power loss to the measurement scanner were detected, and data were interpolated. the change in amplifier v os over the 572 day period for all 30 amplifiers (see figure 38) was less than 100nv, and no clear v os long term drift trend was evident in the data. the excellent long term drift performance is a result of the chopper amplifier?s ability to measure and correct v os errors, leaving only the v os error contribution due to changes in the long term stability of the external components (see figure 39). isl28133 spice model figure 40 shows the spice model schematic and figure 41 shows the net list for the isl28 133 spice model. the model is a simplified version of the actual device and simulates important parameters such as noise, slew rate, gain and phase. the model uses typical parameters from the isl28133. the poles and zeros in the model were determined from the actual open and closed-loop gain and phas e response. this enables the model to present an accurate ac representation of the actual device. the model is configured for ambient temperature of +25c. figures 42 through 49 show the ch aracterization vs simulation results for the noise density, frequency response vs close loop gain, gain vs frequency vs cl and large signal step response (4v). figure 37. long term drift (v os vs time) for 30 units figure 38. long term drift (v os vs time) for a single unit -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 30 60 90 120 180 240 300 360 420 480 540 600 v o s ( v ) time (days) -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 30 60 90 120 180 240 300 360 420 480 540 600 v o s ( v ) time (days) - + 10 1k v out 100k 10 100k figure 39. long term drift test circuit +2.5v -2.5v a cl = 10kv/v
isl28133 fn6560 rev.7.00 page 13 of 20 sep 26, 2015 + - + - i1 i2 m1 m2 r2 r1 r3 r4 en r21 r22 dn1 v15 dn2 v16 cin1 cin2 vin+ vin- 7 13 12 4 7 13 12 4 + - + - + - + - 7 vv3 16 4 + - + - + - + - g2 g1 r6 r5 d1 v3 v4 d2 g4 g3 r8 r7 c1 c2 d3 v5 v6 d4 7 4 16 vv3 + - + - + - + - + - + - e1 g5 g5 r12 r11 l1 r10 r9 l2 g7 g8 r14 r13 c4 c3 g9 g10 d5 d6 d7 d8 g11 g10 r16 r15 v+ vout v- voltage noise input stage gain stage sr limit & first pole pole output stage zero/pole figure 40. spice circuit schematic
isl28133 fn6560 rev.7.00 page 14 of 20 sep 26, 2015 * isl28133 macromodel * revision b, april 2009 * ac characteristics, voltage noise * connections: +input * | -input * | | +vsupply * | | | -vsupply * | | | | output * | | | | | .subckt isl28133 3 2 7 4 6 * *voltage noise d_dn1 102 101 dn d_dn2 104 103 dn r_r21 0 101 120k r_r22 0 103 120k e_en 8 3 101 103 1 v_v15 102 0 0.1vdc v_v16 104 0 0.1vdc * *input stage c_cin1 8 0 0.4p c_cin2 2 0 2.0p r_r1 9 10 10 r_r2 10 11 10 r_r3 4 12 100 r_r4 4 13 100 m_m1 12 8 9 9 pmosisil + l=50u + w=50u m_m2 13 2 11 11 pmosisil + l=50u + w=50u i_i1 4 7 dc 92ua i_i2 7 10 dc 100ua * *gain stage g_g1 4 vv2 13 12 0.0002 g_g2 7 vv2 13 12 0.0002 r_r5 4 vv2 1.3meg r_r6 vv2 7 1.3meg d_d1 4 14 dx d_d2 15 7 dx v_v3 vv2 14 0.7vdc v_v4 15 vv2 0.7vdc * *sr limit first pole g_g3 4 vv3 vv2 16 1 g_g4 7 vv3 vv2 16 1 r_r7 4 vv3 1meg r_r8 vv3 7 1meg c_c1 vv3 7 12u c_c2 4 vv3 12u d_d3 4 17 dx d_d4 18 7 dx v_v5 vv3 17 0.7vdc v_v6 18 vv3 0.7vdc * *zero/pole e_e1 16 4 7 4 0.5 g_g5 4 vv4 vv3 16 0.000001 g_g6 7 vv4 vv3 16 0.000001 l_l1 20 7 0.3h r_r12 20 7 2.5meg r_r11 vv4 20 1meg l_l2 4 19 0.3h r_r9 4 19 2.5meg r_r10 19 vv4 1meg *pole g_g7 4 vv5 vv4 16 0.000001 g_g8 7 vv5 vv4 16 0.000001 c_c3 vv5 7 0.12p c_c4 4 vv5 0.12p r_r13 4 vv5 1meg r_r14 vv5 7 1meg * *output stage g_g9 21 4 6 vv5 0.0000125 g_g10 22 4 vv5 6 0.0000125 d_d5 4 21 dy d_d6 4 22 dy d_d7 7 21 dx d_d8 7 22 dx r_r15 4 6 8k r_r16 6 7 8k g_g11 6 4 vv5 4 -0.000125 g_g12 7 6 7 vv5 -0.000125 * .model pmosisil pmos (kp=16e-3 vto=10m) .model dn d(kf=6.4e-16 af=1) .model dx d(is=1e-18 rs=1) .model dy d(is=1e-15 bv=50 rs=1) .ends isl28133 figure 41. spice net list
isl28133 fn6560 rev.7.00 page 15 of 20 sep 26, 2015 characterization vs simulation results figure 42. characterized input noise voltage density vs frequency figure 43. simulated input noise voltage density vs frequency figure 44. characterized freq uency response vs closed loop gain figure 45. simulated frequency response vs closed loop gain figure 46. characterized gain vs frequency vs c l figure 47. simulated gain vs frequency vs c l frequency (hz) 10 100 1000 input noise voltage (nv/?hz 0.001 0.01 0.1 1 10 100 1k 10k 100k v+ = 5v av = 1 frequency (hz) 10 100 1000 input noise voltage (nv/?hz 0.1 1 10 100 1k 10k 100k v + = 5v a v = 1 -10 0 10 20 30 40 50 60 70 10 100 1k 10k 100k 1m 10m frequency (hz) gain (db) a v = 1 a v = 10 a v = 100 a v = 1000 v + = 5v v out = 10mv p-p c l = 3.7pf r l = 100k r g = 10k, r f = 100k r g = 100, r f = 100k r g = 1k, r f = 100k r g = open, r f = 0 10 100 1k 10k 100k 1m 10m frequency (hz) av = 1 av = 10 av = 100 av = 1000 rg = 1k, r f = 100k rg = 100, r f = 100k rg = 10m r f = 1 rg = 10k, r f = 100k -10 0 10 20 30 40 50 60 70 gain (db) frequency (hz) normalized gain (db) -10 -8 -6 -4 -2 0 2 4 6 8 10k 100k 1m 10m 1k 100 v+ = 5v rl = 100k av = +1 vout = 10mvp-p c l = 824pf c l = 224pf c l = 474pf c l = 51pf c l = 3.7pf c l = 104pf c l = 824pf c l = 474pf cl = 224pf c l = 824pf c l = 3.7pf frequency (hz) -10 -8 -6 -4 -2 0 2 4 6 8 10k 100k 1m 10m 1k 100 c l = 224pf normalized gain (db)
fn6560 rev.7.00 page 16 of 20 sep 26, 2015 isl28133 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2009-2015. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. figure 48. characterized large signal step response (4v) figure 49. simulated large signal step response (4v) characterization vs simulation results (continued) time (s) large signal (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 50 100 150 200 250 300 350 400 v + = 5v r l = 100k a v = 1 c l = 3.7pf v out = 4v p-p v out v in time (s) large signal (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 50 100 150 200 250 300 350 400
isl28133 fn6560 rev.7.00 page 17 of 20 sep 26, 2015 v about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change september 16, 2015 fn6560.7 updated orde ring information table on page 2. updated about intersil verbiage. february 19, 2014 fn6560.6 updated location of note references. added isl28133csensev1z to ordering information table on page 2. may 31, 2011 fn6560.5 changed minimum operating supply voltag e from +1.65v to +1.8v throughout entire datasheet. added tjc information for 5 ld sot-23 pack age in thermal information on page 5. february 1, 2011 fn6560.4 -converted to updated intersil template. -page 1 graphics numbered as figures 1 and 2. -updated ordering information on pa ge 2 by adding part isl28133fhz-t7a. -changed note on page 5, which read ?parameters with min and/or max limits ar e 100% tested at +25c, unless otherwise specified. temperature limits establishe d by characterization and are not production tested.? to ?compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.? -added two long term drift curves (figures 37 and 38) and section ?long term vos drift? on page 12 -replaced pod mdp0038 (no dimension changes), now obsolete with p5.064a. may 3, 2010 fn6560.3 title page 1: replaced ?zero-drift? wi th ?chopper stabilized? for title and part description on page 3: pin configuration: mtdfn -> utdfn on page 7: figure 12: changed 0.1hz to 0.01hz in figure caption on page 11: in ?functional description?; paragraph 1, 2nd sentence: changed text from "?open loop gain (200d b)?" -to- "?open lo op gain (174db)?" changed typ for ?open loop gain? on page 4 from 200db to 174db. on page 11: in ?high gain, precision dc-coupl ed amplifier?; paragraph 2, 1st sentence: changed text from "...dc output error of only 80mv with a maximum temperature drift of 0.75v/c." to "? dc output error of only 80mv with a maximum temperature drift of 0.75mv/c." february 24, 2010 removed ?coming soon? from isl28133eval1z in the ordering information table on pg 2. september 24, 2009 fn6560.2 converted to new intersil template. remo ved isl28233 and isl28433 from data sheet, added applications , related literature, typical application circuit, performance curve, updated ordering information by removing ?coming soon? on sc70 and utdfn packages and adding eval board listed as ?coming soon?. added block diagram, changed in abs max rating voltage from ?5.75v? to ?6.5v?. removed tjc from thermal information until provided by packaging scheduled for 9-11-09. changed low offset ?drift? to low offset ?tc?, added max junction temp 140c, added spice model and simulation results, removed supply current graph at +-3v, re-ordered typical perf ormance curves, removed guard ring information from application section. added revision history and products information may 29, 2009 fn6560.1 page 4: removed the rl = 100 curve from figures 3, 4 and 5. page 1: under features, removed the word "output" from "low output noise" march 25, 2009 fn6560.0 initial release
isl28133 fn6560 rev.7.00 page 18 of 20 sep 26, 2015 small outline transistor plastic packages (sc70-5) d e 1 e e1 c l c c l e b c l a2 a a1 c l 0.20 (0.008) m 0.10 (0.004) c c -c- seating plane 4 5 123 view c view c l r1 r 4x ? 1 4x ? 1 gauge plane l1 seating ? l2 c plane c base metal with c1 b1 plating b 0.4mm 0.75mm 0.65mm 2.1mm typical recommended land pattern p5.049 5 lead small outline transistor plastic package symbol inches millimeters notes min max min max a 0.031 0.043 0.80 1.10 - a1 0.000 0.004 0.00 0.10 - a2 0.031 0.039 0.80 1.00 - b 0.006 0.012 0.15 0.30 - b1 0.006 0.010 0.15 0.25 c 0.003 0.009 0.08 0.22 6 c1 0.003 0.009 0.08 0.20 6 d 0.073 0.085 1.85 2.15 3 e 0.071 0.094 1.80 2.40 - e1 0.045 0.053 1.15 1.35 3 e 0.0256 ref 0.65 ref - e1 0.0512 ref 1.30 ref - l 0.010 0.018 0.26 0.46 4 l1 0.017 ref. 0.420 ref. - l2 0.006 bsc 0.15 bsc ? 0 o 8 o 0 o 8 o - n5 55 r 0.004 - 0.10 - r1 0.004 0.010 0.15 0.25 rev. 3 7/07 notes: 1. dimensioning and tolerances per asme y14.5m-1994. 2. package conforms to eiaj sc70 and jedec mo-203aa. 3. dimensions d and e1 are exclusiv e of mold flash, protrusions, or gate burrs. 4. footlength l measured at reference to gauge plane. 5. ?n? is the number of terminal positions. 6. these dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. controlling dimension: millime ter. converted inch dimen- sions are for reference only.
isl28133 fn6560 rev.7.00 page 19 of 20 sep 26, 2015 package outline drawing l6.1.6x1.6 6 lead ultra thin dual flat no-l ead col plastic package (utdfn col) rev 1, 11/07 typical recommended land pattern detail "x" top view bottom view side view located within the zone indica ted. the pin #1 i dentifier may be unless otherwise specified, t olerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of t he pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the meta llized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 1.60 5x 0 . 40 0 . 1 0.15 ( 1 . 4 ) (4x) ( 6x 0 . 25 ) ( 1x 0 .70 ) ( 4x 0 . 5 ) 0 . 55 max base plane c seating plane 0.08 c 0.10 c 0.25 +0.05 / -0.07 see detail "x" 0.10 4 ca mb index area 6 pin 1 1.60 a b pin #1 index area 0.50 2x 1.00 4x 6 ( 5x 0 . 60 ) 0 . 00 min. 0 . 05 max. c 0 . 2 ref 4 3 6 1 1x 0.5 0.1
isl28133 fn6560 rev.7.00 page 20 of 20 sep 26, 2015 package outline drawing p5.064a 5 lead small outline transistor plastic package rev 0, 2/10 dimension is exclusive of mold flash, protrusions or gate burrs . this dimension is measured at datum h. package conforms to jedec mo-178aa. foot length is measured at r eference to guage plane. dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "x" side view typical recommended land pattern top view index area pin 1 seating plane gauge 0.450.1 (2 plcs) 10 typ 4 1.90 0.40 0.05 2.90 0.95 1.60 2.80 0.05-0.15 1.14 0.15 0.20 c a-b d m (1.20) (0.60) (0.95) (2.40) 0.10 c 0.08-0.20 see detail x 1.45 max (0.60) 0-3 c b a d 3 3 3 0.20 c (1.90) 2x 0.15 c 2x d 0.15 c 2x a-b (0.25) h 5 2 4 5 5 end view plane

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